/*
 * Copyright 2010 Emmanuel Roussel
 * http://rousselmanu.free.fr
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License as published by
 * the Free Software Foundation; either version 2, or (at your option)
 * any later version.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; see the file COPYING.  If not, write to
 * the Free Software Foundation, Inc., 51 Franklin Street,
 * Boston, MA 02110-1301, USA.
 */

#include <cc1110.h>
#include "types.h"			//u8
#include "ioCCxx10_bitdef.h"	//all the defines for MCSM0, MARCSSTATE, ...

void setup_radio(void){
	
   /* Set up radio. These settings are obtained from SmartRF® Studio.
     * The settings are default values for "Simple RX" mode.
     */
    FSCTRL1   = 0x0A;   // Frequency synthesizer control.
    FSCTRL0   = 0x00;   // Frequency synthesizer control.
    FREQ2     = 0x5D;   // Frequency control word, high byte.
    FREQ1     = 0x93;   // Frequency control word, middle byte.
    FREQ0     = 0xB1;   // Frequency control word, low byte.
    MDMCFG4   = 0x86;   // Modem configuration.
    MDMCFG3   = 0x83;   // Modem configuration.
    MDMCFG2   = 0x03;   // Modem configuration.
    MDMCFG1   = 0x22;   // Modem configuration.
    MDMCFG0   = 0xF8;   // Modem configuration.
    CHANNR    = 0x00;   // Channel number.
    DEVIATN   = 0x44;   // Modem deviation setting (when FSK modulation is enabled).
    FREND1    = 0x56;   // Front end RX configuration.
    FREND0    = 0x10;   // Front end RX configuration.
    MCSM0     = 0x14;   // Main Radio Control State Machine configuration.
    FOCCFG    = 0x16;   // Frequency Offset Compensation Configuration.
    BSCFG     = 0x6C;   // Bit synchronization Configuration.
    AGCCTRL2  = 0x03;   // AGC control.
    AGCCTRL1  = 0x40;   // AGC control.
    AGCCTRL0  = 0x91;   // AGC control.
    FSCAL3    = 0xA9;   // Frequency synthesizer calibration.
    FSCAL2    = 0x0A;   // Frequency synthesizer calibration.
    FSCAL1    = 0x00;   // Frequency synthesizer calibration.
    FSCAL0    = 0x11;   // Frequency synthesizer calibration.
    TEST2     = 0x88;   // Various test settings.
    TEST1     = 0x31;   // Various test settings.
    TEST0     = 0x09;   // Various test settings.
    PA_TABLE0 = 0xFE;   // PA output power setting.
    PKTCTRL1  = 0x04;   // Packet automation control.
    PKTCTRL0  = 0x04;   // Packet automation control.
    ADDR      = 0x00;   // Device address.
    PKTLEN    = 0xFF;   // Packet length.

    /* Radio setting not from SmartRF® Studio:
     * - Keep the radio in RX.
     * - Auto calibrate when going from IDLE to RX or TX (or FSTXON).
     */
    MCSM1 = (MCSM1 & ~MCSM1_RXOFF_MODE) | MCSM1_RXOFF_MODE_RX;
    MCSM0 = (MCSM0 & ~MCSM0_FS_AUTOCAL) | FS_AUTOCAL_FROM_IDLE;

    /* Radio is now in IDLE.
       Strobe command SRX takes radio to RX. */
    RFST = RFST_SRX;

    /* Wait until RX is entered. */
    while ((MARCSTATE & MARCSTATE_MARC_STATE) != MARC_STATE_RX);

    /* Wait a little longer than expected RSSI response time
     * (see design note DN505). Note that the below loop is inaccurate,
     * so the user must implement a proper delay according to DN505.
     */
    //for(rssiValidCnt = 0; rssiValidCnt < RSSI_VALID_TIME; rssiValidCnt++);


}

void init_rand(){
	/* Seeding the random generator by writing the RSSI value to the RNDL
     * register (twice). The seed could be made more random, e.g. by combining
     * several RSSI samples and/or not writing the same value twice to RNDL.
     */
	u8 seed = RSSI;
    RNDL = seed;
    RNDL = seed;
}

u8 rand(void){
	//u16 rndNumber;
	/* Clock the LFSR once (13x unrolling) to generate pseudo-random bytes. */
	ADCCON1 = (ADCCON1 & ~ADCCON1_RCTRL) | ADCCON1_RCTRL_LFSR13;

	/* Waiting for operation to complete (RCTRL = 00). */
	while (ADCCON1 & ADCCON1_RCTRL_COMPL);

	/* Storing the random number, debug to see the value.
	 * Done in two statements to define the order of volatile accesses.
	 */
	//rndNumber = RNDL;
	//rndNumber |= RNDH << 8;
	
	return RNDL;//(u8)rndNumber&0xFF;
}
